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verilog-instance.vim : Create SystemVerilog port instantiation from port declaration.

 script karma  Rating 17/7, Downloaded by 851  Comments, bugs, improvements  Vim wiki

created by
Antoine Madec
 
script type
utility
 
description
verilog-instance.vim
====================

Create SystemVerilog port instantiation from port declaration.
Work on modules, tasks, functions and all other similar structures.

https://raw.githubusercontent.com/antoinemadec/gif/master/veriloginstance.gif

Project home (latest version):
https://github.com/antoinemadec/vim-verilog-instance

Quick start guide
-----------------

try these commands:

- gbi(
    - Start VerilogInstance command (gb) for inner parenthesis
- vjjgb
    - visual-select, down twice
    - Start VerilogInstance command (gb) on the 3 selected lines

Other vim plugins for Verilog/SystemVerilog
---------------------------------------

verilog_systemverilog: https://github.com/vhda/verilog_systemverilog.vim is a syntax plugin for Verilog and SystemVerilog

Author
------

Antoine Madec: https://github.com/antoinemadec

License
------

Copyright (c) Antoine Madec. Distributed under the same terms as Vim itself. See :help license.
 
install details
Use your favorite plugin manager. Using vim-plug:
Plug 'antoinemadec/vim-verilog-instance'
 

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script versions (upload new version)

Click on the package to download.

package script version date Vim version user release notes
vim-verilog-instance-1.0.zip 1.0 2017-09-19 7.0 Antoine Madec Initial upload
ip used for rating: 35.175.113.125

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