created by

MingZhi Li

script type

indent

description

" Title:        Verilog HDL/SystemVerilog HDVL indent file " Maintainer: Mingzhi Li <limingzhi05@mail.nankai.edu.cn> " Last Change: 2007-12-16 20:10:57 CST " " Buffer Variables: "     b:verilog_indent_width   : indenting width(default value: shiftwidth) " " Install: "     Drop it to ~/.vim/indent " " URL: "    http://www.vim.org/scripts/script.php?script_id=2091 " " Revision Comments: "     Mingzhi Li  2007-12-16 20:09:39 CST Version 1.2       "        Bug fixes "     Mingzhi Li  2007-12-13 23:47:54 CST Version 1.1       "        Bug fix, improve performance and add introductions "     Mingzhi Li  2007-12-7  22:16:41 CST Version 1.0   "        Initial version "       " Known Limited: "     This indent file can not work well, when you break the long line into "     multi-line manually, such as: "      always @(posedge a or posedge b "          or posedge c ) begin "         //... "      end "     Recommend to use the coding style(wraped by vim automatically) as following: "       always @(posedge a or posedge b or posedge c ) begin "         //... "       end

install details

Drop it to ~/.vim/indent

Click on the package to download.

package	script version	date	Vim version	user	release notes
verilog.vim	1.3	2012-03-13	7.0	MingZhi Li	Bugfixs
verilog.vim	1.2	2007-12-16	7.0	MingZhi Li	Bug fixes
verilog.vim	1.1	2007-12-13	7.0	MingZhi Li	Bug fix, improve performance and add introductions
verilog.vim	1.0	2007-12-12	7.0	MingZhi Li	Initial upload

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