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automatic for Verilog & RtlTree : Automatic generator for Verilog HDL (upgraded) & RtlTree

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created by
zhang guo
script type
upgrade form   "http://www.vim.org/scripts/script.php?script_id=2372

Support Automatic functions like Emacs for Verilog HDL

Date: 2017-09-18 upload.

    For write verilog code more automatic.
    Like Emacs for Verilog HDL.

Use it in gvim.

File path:
    vim/.vim/plugin/automatic.vim   -- vim script
    vim/.vim/after                  -- icon images

use in gvim normal mode:

AutoTemplate    -- Add simple format code in *.v.
                   include: AutoHeader ...
                   setenv in your .cshrc for AutoHeader:
                       setenv COMPANY "your company name"
                       setenv USER_DIT "your alias name"
<F2>            -- Comment/un-Comment single line with simple info.  -- with //
<F3>            -- Comment/un-Comment multi  line,  -- with /*  ... */
                   use <Ctrl-V> select multi lines, then <F3>
<F4>            -- Add a comment at end of current line

<Shift-F1>      -- AutoArg, Auto fill module module port arg(same as Emacs).
                   below line /*autoarg*/
<Shift-F2>      -- Auto Define Signals,
                   below line /*autodef*/
<Shift-F3>      -- Auto Instance.   -- line with /*autoinst*/
                   goto module instantiation line, the <Shift-F3>.
                   It is more useful.
                   -- sometimes with bug, please re-open .v file.

:RtlTree        -- Like Verdi.
                   Left-Click:  go to specified sub-module instance line.
                   Left-DoubleClick / Enter Key:  go to specified module define line.
                   <Crtl-Alt-A>: go to hierarchical module instantiation line.
                   <Crtl-Alt-N>: go to hierarchical module define line.
                   -- Verdi is more powerful, so ...

Icon shortcut in gvim GUI upper-rigth:
PN: always @(posedge clk or negedge rst_n)
* : always @(*)
NN: always @(negedge clk or negedge rst_n)
ShowCall: goto current sub-modue instance line in parent module source file.
             -- only use in RtlTree have open.
ShowDef : goto current sub-modue source file. -- only use in RtlTree have open.

Some function base on tags.
You may need update tags with ctags_gen script with all your *.v file.
ctags_gen *.v    or
ctags_gen -L verilog_file.lst

You can modify this automatic.vim for your want.

//         version info before 2014.

=  Install

1. vim version need >= 7.0
2. copy automatic.vim to your home directory .vim/plugin/
3. decompress Draw_pixmaps.rar, copy *.xpm file to .vim/after,
   if directory no exist, create it.
4. modify your vim config file .vimrc:
   set fileformat=unix
   syntax on

   set expandtab        " use <space> char replace <tab> char

   set shiftwidth=4
   set tabstop=4
   set ruler
   set smartindent
   set incsearch
   set hlsearch

   map <F4> :RtlTree<CR>
   map <F5> <C-w><C-w>

   " save cursor position at exit edit file
   autocmd BufReadPost *
       \ if (line("'\"") > 0 && line("'\"") <= line("$") |
       \    exe "normal g`\"" |
       \ endif

=  Usage

== Automatic for Verilog

1. Auto Argument,         :call AutoArg()   or shortcut key <Shift>+<F1>
2. Auto Definition,       :call AutoDef()   or shortcut key <Shift>+<F2>
3. Auto Instance,         :call AutoInst(0) or shortcut key <Shift>+<F3>  "key words /*autoinst*/
4. Auto Comment,
     single line comment, :call AutoComment()  or shortcut key <F2>
     multi line comment,  :call AutoComment2() or shortcut key <F3>
5. "Always @" block quick input template, leftclick icon "AL**"
6. abbrev "<=" to "<= #1" in insert mode

== Draw wave

1. leftclick icon "CLK" to create a clock signal wave
2. leftclick icon "SIG" to create a one-bit signal wave
3. leftclick icon "BUS" to create a bus signal wave
4. leftclick icon "SEP" to create a blank line
5. leftclick icon "NEG" to add a flag char 'neg' to end of one sig
6. to draw wave use shortcut key <F8>

note: goto bottom line of sig line(total 3 lines) to create a new sig/blank line

== RtlTree

1. Only use in gvim
2. use script ctags_gen to create file tags, rtltree work need file tags
3. Use like Verdi

=  Limit

1. One design unit per file

        A file must not contain more than one design unit. Everything contained in a design
     unit must be completely contained in a single module/endmodule construct.

2. File naming conventions

    The file name must be composed in the following way:
    <design unit name>.v

    <design unit name> is the name of the design unit (i.e., module name).

    example: spooler.v Synthesizable Verilog code for module spooler

install details

rate this script Life Changing Helpful Unfulfilling 
script versions (upload new version)

Click on the package to download.

package script version date Vim version user release notes
automatic_vim_2017_09_18.tar.gz 2.2.4 2017-09-18 7.0 zhang guo clear a AutoInstUpdate INST_DEL problem for null comma inst port line
automatic_vim_2017_09_16.tar.gz 2.2.3 2017-09-16 7.0 zhang guo UPDATE:
1. clear a AutoArg bug
2. resume AutoInst*(1) function for multi-times instance & update
automatic_vim_2017_08_28.tar.gz 2.2.1 2017-08-28 7.0 zhang guo clear a AutoInstPortReAlign bug
automatic_vim_2017_08_27.tar.gz 2.20 2017-08-27 7.0 zhang guo 1. Add New AutoInstUpdate series function
        a) AutoInstUpdate
               Update module instance, detect the Newst append and have deleted module ports
               It is very useful for RTL code module instance update.
        b) AutoInstUpdateOrder
               Update module instance, instance port order same with module port.
               It is very useful for RTL code module instance update.
        c) AutoInstPortReAlign
               Auto Inst Port signal auto Re-Align format, only Re-Align port connection
        d) AppendPortDriectionToInst
               Append port direction info(comment) to have instanced module port instanced line

2. CreateRtlTree update
        use verilog "()" & "{}" pair to skip module define block, skip always block, Concatenate block and so on

automatic_vim_2017_01_01.tar.gz 2.1.0 2017-01-01 7.0 zhang guo 1. get sub-instance algorithm modify, use verilog 2001 syntax Module instantiation
   replace old algorithm (use keywords autoinst)
2. function ShowCall & ShowDef update
3. rtltree little upgrade, support `ifdef `ifndef `elsif `else `endif in rtltree
automatic_vim_2016_08_24.tar.gz 2.0.1 2016-08-24 7.0 zhang guo 1. add Search menu, -- search instance / module / Trace Driver(Lite)
   -- for the Search & Trace, add backward & forward history feature like verdi
2. some function short-cut key modify
automatic_vim_2016_02_27.tar.gz 2.0.0 2016-02-27 7.0 zhang guo upload after more than one year.
automatic_v1.4.rar v1.4 2013-12-21 7.0 zhang guo 1. Add always block quick input template
2. clr rtltree no definition g: variable bug (NERDTree)
3. update Draw wave for negedge toggle logic
4. update FileHeader for .v file
automatic_v1.3.rar 1.3 2013-02-09 7.0 zhang guo rtltree support tree fold, it's init_max_display_layer is 3
automatic_v1.2.3.rar 1.2.3 2013-01-11 7.0 zhang guo fix some bugs on function AutoDef
automatic.rar 1.2.2 2012-11-21 7.0 zhang guo fix AutoArg bug
fix AutoInst bug (function GetIO)
automatic.rar 1.2.1 2012-10-30 7.0 zhang guo add icon for DrawTiming, only use in gvim.  Usage: decompress Draw_pixmaps.rar , modify the icon file path in file automatic.vim
automatic1.2.rar 1.2 2012-08-04 7.0 zhang guo new add RtlTree  
   - it's useful, refrence NERDTree source code, work like EDA tool verdi.
automatic.rar v1.1 2012-06-09 7.0 zhang guo upgrade a little, and clr a bug about autodef
automatic.rar 1.01 2012-05-14 7.3 zhang guo append file: ctags_gen
automatic.rar 1.00 2012-05-14 7.0 zhang guo Initial upload
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