created by

jun wang

script type

utility

description

You can get latest version from https://github.com/kdurant/verilog-testbench Feature Auto generate testbench about current file Auto generate component instance about current file Rapid input verilog port, reg and wire This plugin don't check your syntax whether is corrected. You should invoke compiler to do it before use this plugin.

install details

Installation This plugin follows the standard runtime path structure, and as such it can be installed  plugin manager :     Pathogen     $ cd ~/vimfiles/bundle     $ git clone https://github.com/kdurant/verilog-testbench.git verilog-testbench      manual:     copy all of the files into your ~/vimfiles/directory

Click on the package to download.

package	script version	date	Vim version	user	release notes
testbench-2.4.zip	2.4	2013-09-06	7.0	jun wang	add insert function you can rapid input verilog port, reg and wire
testbench.zip	2.3	2013-09-02	7.0	jun wang	align port that instanced
testbench.rar	2.2	2013-08-28	7.0	jun wang	add instance function
verilog_testbench.rar	2.1	2013-08-21	7.0	jun wang	fix some bugs
testbench.zip	2.0	2013-08-21	7.0	jun wang	rewrite it
verilog_auto_testbench.vim	1.1	2013-05-23	7.3	jun wang	Fixed the missing port width problem
verilog_auto_testbench.vim	1.0	2013-05-23	7.3	jun wang	Initial upload

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