created by

Aditya Kher

script type

syntax

description

IEEE 1800 SystemVerilog is the industry's first unified hardware description and verification language (HDVL) standard. SystemVerilog is a major extension of the established IEEE 1364 Verilog language. cheers!

install details

Step 1: drop the file in ~/.vim/syntax (if the directory does not exist then create it)              Note: If you are using vim 7.0 or better, you can source SV.vba to autoinstall it regardless of which flavor of              operating system you are using VIM on!! Step 2: Append following lines in ~/.vim/filetype.vim if exists("did_load_filetypes")           finish         endif         augroup filetypedetect           au! BufRead,BufNewFile *.sv    setfiletype SV           au! BufRead,BufNewFile *.svi   setfiletype SV         augroup END

Click on the package to download.

package	script version	date	Vim version	user	release notes
sv.vba	1.3	2008-06-12	7.0	Aditya Kher	vba for VIM 7.0 or better
sv.vim	1.2	2008-06-12	6.0	Aditya Kher	vim 6 or better compatibility

ip used for rating: 3.145.175.243