signal_dec_VHDL : Defines internal signals in VHDL
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Vim wiki
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| created by |
| Sunil Shukla |
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| script type |
| utility |
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| description |
| This utility defines an internal signal in VHDL. It map the function to key combination ,,. Within the architecture region, do ,, in visual mode and you will be prompted for the length of the signal. Only works for std_logic and std_logic_vector. |
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| install details |
| copy the file anywhere and source it in your _vimrc. |
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