verilog_auto_testbench : auto generate testbench and component instance current design unit
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|You can get latest version from https://github.com/kdurant/verilog-testbench
Auto generate testbench about current file
Auto generate component instance about current file
Rapid input verilog port, reg and wire
This plugin don't check your syntax whether is corrected. You should invoke compiler to do it before use this plugin.
This plugin follows the standard runtime path structure, and as such it can be installed plugin manager :
$ cd ~/vimfiles/bundle
$ git clone https://github.com/kdurant/verilog-testbench.git verilog-testbench
copy all of the files into your ~/vimfiles/directory
Click on the package to download.
ip used for rating: 18.104.22.168